Synchronization in All-digital Qam Receivers

The recent advance in Field Programmable Gate Array (FPGA) technology hasbeen largely embraced by the communication industry, which views this technology asan effective and economical alternative to the design of Application Specific IntegratedCircuits (ASICs). The primary reasons for switching to FPGAs are lower developmentand non-recurring engineering costs, the flexibility to design to a preliminary standardand adapt the design as the standard evolves, as well as the option of performingsoftware updates in the field.A sector with strong interest in FPGAs is the coaxial cable TV/Internet distrib-ution industry. The creation of soft preliminary standards by the standards organi-zation governing the industry has been the main catalyst for the massive adoption ofFPGAs by small to medium size companies, which see this technology as an oppor-tunity to compete in this open market.Both the circuit speed and the economy of FPGA technology depend upon usingalgorithms that map efficiently into its fabric. Often it is prudent to sacrifice per-formance to improve either clock speed or economy when developing with FPGAs.The purpose of this research is to both revise and devise synchronization algorithms/ structures for cable digital receivers that are to be implemented in FPGA.The main communication scheme used by the coaxial cable distribution industry isdigital Quadrature Amplitude Modulation (QAM). The problem of synchronizing tothe QAM signal in the receiver is not a new topic and several synchronization-relatedcircuits, which were devised with ASICs implementation in mind, can be found inthe open literature. Of interest in this thesis is the non-data-aided digital timingsynchronizer that was proposed by D’Andrea to recover timing with no knowledgeof the transmitted data. Accurate timing estimation was achieved by reshaping thereceived signal with a prefilter prior to estimating the timing.